The present invention relates to an output control scan flip-flop, a semiconductor integrated circuit including the same, and a design method for the semiconductor integrated circuit.
In a scan test which is one of test methods of semiconductor integrated circuits, extremely large amount of electric power is consumed compared to a normal operation. Therefore, reduction of a peak of power consumption (hereinafter referred to as peak power consumption) at the time of the scan test is required.
In the meantime, operation speeds of recent semiconductor integrated circuits have been extremely increasing. Accordingly, it is required to prevent reduction of the operating speed at the time of the normal operation by circuit correction for the purpose of reducing peak power consumption at the time of the scan test.
One solution to such a problem is disclosed in Japanese Unexamined Patent Application Publication No. 2009-175154. As shown in FIG. 10, a semiconductor integrated circuit disclosed in Japanese Unexamined Patent Application Publication No. 2009-175154 corrects a scan flip-flop 501 which is selected as a flip-flop which gives a large influence on power consumption at the time of the shift operation of the scan test so that an output value to a combination circuit 502 is fixed during the shift operation of the scan test. Further, this semiconductor integrated circuit suppresses an increase of an area to an allowable range by limiting the number of scan flip-flops selected as a flip-flop which gives a large influence on power consumption at the time of the shift operation of the scan test based on an increment of the area that is allowed at the time of the circuit correction. Further, this semiconductor integrated circuit does not select the flip-flop which is the start point of a path between flip-flops for determining the operating speed of the circuit, thereby preventing the influence given to the function operation (normal operation).